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*****For immediate use May 15th, 2000

NEC Electronics Achieves Key Milestone in ACE-2 Initiative;Reduces System-Level Turnaround Time by More Than 30 Percent

Company Also Unveils Second Phase of Its Open System Design Methodology

TOKYO May 15th, 2000- NEC Corporation (NEC)* (NASDAQ: NIPNY) (FTSE: 6701q.l) today announced that its subsidiary NEC Electronics Inc.,* has completed phase 1 of a system-on-a-chip (SOC) open system design methodology initiative, code-named ACE-2. As a result of phase 1, NEC Electronics has reduced system-level design turnaround time for SOC designs by one-third - from an average of 450 engineering months to 300 months.

Also today, NEC unveiled its EDA partners for the first phase of the ACE-2 initiative which include Cadence Design Systems, CARDTools Systems, CoWare, Mentor Graphics, Synopsys, Synplicity, Tera Systems and Verisity. (Please see individual press releases from EDA partners, also released today)

Additionally, NEC Electronics disclosed its plans for phase 2 of the ACE-2 initiative. In phase 2, the company will focus on hardware design, system analysis and market-based design.

"With the ACE-2 initiative, we set out to establish an open system design methodology that would reduce system-level design turnaround time by two-thirds," said Kazu Yamada, general manager of the Technology Foundation Division, NEC Electronics Inc. "Within phase 1, we reduced design time by one-third and are well on our way to accomplishing our overall goal. As we move ahead to phase 2, we will now address the emerging design challenges that threaten the productivity of our customers' design teams."

Phase 1 Reduces Design Turnaround by More Than 30 Percent

Phase 1 of the ACE-2 initiative at NEC Electronics focused on five elements in the overall SOC design flow that significantly impact the turnaround time for SOCs. For each element, NEC Electronics identified and recommended key EDA tools to enable a new design methodology. Moving forward, the company will team with customers to help them adopt this new design flow. The specific design areas addressed by phase 1 include:

  • IP Modeling:
    NEC Electronics developed a new IP core methodology and created IP models. The resulting IP models are portable for multiple designs and can be used for hardware and software verification.

  • Software Verification:
    In the conventional ASIC design flow, designers use hardware/software verification tools that can be very slow due to the speed of RTL simulators. Using C/C++ abstracted hardware models, NEC Electronics established software/firmware verification in the early stage of design to speed the verification process by 100X.

  • Fast RTL Verification:
    Because verification is the largest bottleneck in the ASIC design flow, NEC Electronics identified a method for fast RTL (register transfer level) and has been able to reduce verification time by 2X on average.

  • Interface to Silicon Design:
    NEC Electronics' new design flow enables easy interface to silicon design using a design planning tool. This step of the design flow dramatically reduces design turnaround time and improves the quality of silicon results by accelerating timing convergence at high clock frequencies and by enabling an RTL signoff methodology.

  • System Evaluation:
    Using its own COREBESTTM prototyping board, NEC Electronics also established a method for creating an FPGA prototype board to allow for system evaluation and demonstration at the RT level.

NEC Electronics Unveils Goals of Phase 2

While phase 1 focused on improving the design flow to address the most pressing issues facing designers today, phase 2 of ACE-2 proactively addresses new areas of the design flow where tools do not currently exist, such as hardware design, system analysis and market-based design for specific market segments. By the end of phase 2, NEC Electronics expects to reduce design turnaround time from 300 engineering months to only 200 months. To achieve this, NEC Electronics will continue to work with leading EDA vendors.

ACE-2 Initiative

The NEC Electronics ACE-2 program is a three-year, $30 million effort, chartered with the development of a significantly enhanced design environment targeted to reduce overall turnaround time for system-on-a-chip designs. The goal is to offer NEC customers a three-month turnaround time-from system specification to tape-out-for a 30-million gate design by the year 2002. The initiative was introduced in May 1999 as part of NEC Electronics' roadmap for emerging as a leader in providing SOC solutions to the communications, consumer and automotive markets.

Tools developed as part of the ACE-2 initiative will focus on a higher level of design abstraction, including system description, IP models and RTL sign-off. In addition, the resulting design environment will allow concurrent design and early troubleshooting, specifically related to system and performance evaluations and RTL design planning. Each of these capabilities will reduce the time-to-market restrictions currently associated with deep sub-micron designs. The ACE-2 system-level environment will complement NEC's comprehensive back-end design environment, OpenCAD(r), consisting of the industry's best proprietary and third-party design tools.

About NEC's SOC Strategy

NEC offers its customers a path for continued, customized integration, by providing a wide variety of standard products, application specific standard products (ASSPs), application specific custom products (ASCPs) and ASICs-depending on the customers' price, performance and time-to-market requirements. The products in the SOC line-up can be customized for customer needs either immediately or in future generations. The new ACE-2 design environment is expected to enhance NEC's ability to deliver on this promise, by enabling many of its standard products to be developed within the same design environment as its customers' ASICs-making the path to customization even more seamless and efficient.

About NEC Corporation

NEC Corporation (NASDAQ: NIPNY) (FTSE: 6701q.l) is a leading provider of Internet solutions, dedicated to meeting the specialized needs of its customers in the key computer, network and electron device fields through its three market-focused in-house companies: NEC Solutions, NEC Networks and NEC Electron Devices. NEC Corporation, with its in-house companies, employs more than 150,000 people worldwide and saw net sales of 4,759 billion Yen (approx. US$40 billion) in fiscal year 1998-1999.

For further information, please visit the NEC home page at: http://www.nec-global.com

About NEC Electronics Inc.

NEC Electronics Inc., headquartered in Santa Clara, California, is one of the leading developers, manufacturers and suppliers of semiconductor products in the United States. Committed to meeting customers' cost, performance and time-to-market requirements, the company offers solutions ranging from standard products to system-on-a-chip (SOC) solutions, as well as customized products for next-generation designs. NEC Electronics also offers customers the benefits of a state-of-the-art manufacturing facility in Roseville, CA, and the global manufacturing capabilities of its parent company, NEC Corporation (NASDAQ:NIPNY).

For more information about products offered by NEC Electronics Inc., please visit the NEC Electronics Web site at http://www.necel.com.



*: NEC and NEC Electronics Inc. are either registered trademarks or trademarks of NEC Corporation in the United States and/or other countries. All other registered trademarks or trademarks are property of their respective owners.#10768

  • This story originates from NEC Electronics in Santa Clara, California.

[Copyright(C) NEC Corporation 1999. NEC and C&C are trademarks of NEC Corporation.]