[C&C for Human Potential / NEC Corporation]



Core Lineup and List of Specifications for CB-130


  1. Memory macro (SRAM)

    The lineup includes both the 6-transistor cell compiled-type memory in which the bit/word configuration can be customized, which is the mainstream memory for conventional cell-based ICs, and the new loadless 4-transistor cell memory with the high-speed, high-capacity features essential for system LSI.
    (Products currently under development are also included in the lineup.)

    CB-130H library:

    Compiled type
    High-speed
    memory
    Single-port: Up to 144 Kbits (Tcyc = 800 MHz)

    Dual-port: Up to 288 Kbits (Tcyc = 500 MHz)
    Multi-port
    memory
    3 ports (2R/1W): Up to 64 Kbits

    6 ports (4R/2W): Up to 32 Kbits

    Hard macro type
    Large-scale
    memory
    Single-port: 4, 8, 16 Mb(Loadless 4-transistor cell)

    CB-130M library:

    Compiled type
    High-speed
    memory
    Single-port: Up to 144 Kbits (Tcyc = 450 MHz)

    Dual-port: Up to 288 Kbits (Tcyc = 350 MHz)
    High-density
    memory
    Single-port: Up to 2.3 Mb

    Dual-port: Up to 288 Kbits
    Multi-port
    memory
    3 ports (2R/1W): Up to 64 Kbits

    6 ports (4R/2W): Up to 32 Kbits

    Hard macro type
    Large-scale
    memory
    Single-port: 4, 8, 16 Mb(Loadless 4-transistor cell)

    CB-130L library:

    Compiled type
    High-density
    memory
    Single-port: Up to 1 Mbit

    Dual-port: Up to 288 Kbits

  2. Core lineup

    The lineup is aimed at markets that demand high-density, high-speed operation, low power consumption systems, in which the CB-130 Family will play a vital role. (Products currently under development are also included in the lineup.)

    Communications: Network controller, ATM *1, Ethernet, xDSL *2
    Graphics: DRAC *3, 2D/3D accelerator, NTSC/PAL encoder
    Mobile: DSP, speech code
    Digital home
    electronics:
    PCI *4 controller, USB *5, IEEE1394, MPEG2 encoder/decoder, JPEG, modem code
    Common to
    all fields:
    Digital PLL, analog PLL, UART *6, register file, scan, JTAG, FIFO, CAM, ROM, A/D converter, D/A converter, V850E CPU *7, VRxxxx CPU *8

  3. Interface

    Although the internal circuits operate at 1.2 V, NEC has provided 1.8 V, 2.5 V, and 3.3 V full-swing interfaces, as well as a variety of high-speed interfaces additional to the standard CMOS interface block. (Products under development are included in this lineup.) NEC also pledges to provide high-speed interfaces such as SerDes as gigahertz-band interface macros.

    I/O block: LVCMOS/LVTTL
    Low-noise buffer (slew-rate buffer)
    3-state buffer, open-drain buffer
    High-speed interface: GTL+ *9, HSTL *10, PECL *11, SSTL *12, LVDS *13, AGP *14, PCI, PCIX, USB, IEEE1394, SerDes


*1: Asynchronous Transfer Mode.
*2: xDigital Subscriber Line.
*3: Direct Rambus ASIC Cell.
*4: Interface standard recommended by Intel.
*5: Universal Serial Bus.
*6: Universal Asynchronous Receiver Transmitter.
*7: V850 Series 32-bit RISC MPU produced by NEC.
*8: VRxxxx Series 64-bit RISC MPU produced by NEC.
*9: Interface standard recommended by Intel (Gunning Transceiver Logic)
*10: High Speed Transceiver Logic
*11: Pseudo Emitter Coupled Logic
*12: Stub Series Terminated Transfer Logic
*13: Low Voltage Differential Signaling
*14: Accelerated Graphics Port

[Copyright(C) NEC Corporation 1999. NEC and C&C are trademarks of NEC Corporation.]