[C&C for Human Potential / NEC Corporation]

Major Specifications of the V850E CPU Core

Architecture- Thirty-two 32-bit general-purpose registers
- Load/store architecture
- 4G-byte linear address space
- Upward compatibility with the V850 on the object level
- Number of instructions: 81
- 2-byte basic instruction set
- CISC instruction: Bit manipulation instruction, saturated
operation instruction
- Instruction for high-level languages: Instruction for
processing a C Switch statement, table lookup branch
instruction, function start/end processing instruction,
data conversion instruction
Implementation- Five-stage pipelining with one-clock pitch
- Internal 32-bit (32 x 32 -> 64) multiplier
- Hardwired control
- Completely static circuit
- Top-down design approach following the latest trends in
process technologies
Operating frequency- DC to 50 MHz (Up to 40 MHz for the V850E/MS1)
Performance- Minimum instruction execution time: 1 clock
- Integer processing speed: 1.3 MIPS/MHz (VAX11 value
calculated according to the Dhrystone benchmark 1.1)
- Multiplication: 1 to 2 clocks (32 x 32 -> 64 bits)
- Interrupt response time: 5 or more clocks
- Internal memory access:
ROM/RAM instruction fetch: 1 clock (32 bits)
RAM data access: 1 clock (32 bits)

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